Integrated circuit technology is producing circuits with increasing complexity and component density. Elements as small as 1 and 2 microns in size can be produced using an electron image projection system described in U.S. Pat. No. 3,679,497, granted July 25, 1972. As a result, memory cells as small as 1.2 .times. 10.sup.-.sup.6 cm.sup.2 and gate areas as small as 4 .times. 10.sup.-.sup.6 cm.sup.2 are achievable, which should permit fabrication of an enitre 20,000 gate logic, 256,000 bit memory computer on a 1 cm.sup.2 semiconductor wafer.
One of the severely limiting factors on such microminiaturization is the testing procedure necessary to the circuit fabrication. It is practically impossible to manufacture, a defect-free complex integrated circuit. Thus, during and/or after fabrication, the individual segments and modules of the circuit must be separately tested to determine whether the electrical characteristics are in accord with the design values within allowable tolerances. At present, such testing is done with mechanical probes which physically contact the input and output electrodes of the individual segments and modules so that a test device can measure the input and/or output voltage and current.
The problem is that the smallest area of metal which can be satisfactorily contacted mechanically with a fine wire probe system is about 75 .times. 75 microns -- larger than the individual logic gates of a high density integrated circuit. The test points become too numerous and too closely spaced to be mechanically contacted when the circuit is micro-miniaturized. Testing by mechanical probe thus places a limit on the density of the circuit unrelated to fabrication capabilities and limitations.
Further, testing by mechanical probes can cause severe damage to the integrated device. Although fine wire test probes may seem very flexible to a human observer, they are very stiff and heavy relative to the fine structure of integrated circuits. Mechanical probes (i) can contaminate and abrade the device surfaces so that subsequent fabrication steps, e.g. final metalization, cannot be effectively accomplished, and (ii) can exert high localized forces and introduce localized stresses so that active regions of the device are dislocated and distorted. In addition, a mechanical probe can score electrodes and damage oxide layers. Quality control and quantitative yields can, therefore, be increased by eliminating mechanical probes.
A finely-focused electron beam in a vacuum chamber can in some instances be used as a contactless probe in the testing of planar electron devices, and particularly integrated circuits, in place of mechanical contact probes. Under control from a digital computer, the electron beam can be very accurately addressed to coordinate locations on an integrated circuit at high speed. However, the use of an electron beam for contactless testing of integrated circuits is very restricted in its applications.
The use of multiple electron beams in contactless testing is virtually impossible. The apparatus for such multiple beams is bulky and requires separate control of the beams. Further, tremendous difficulty is encountered in isolation of the beams and in accurately addressing the beams relative to each other. As a result, only a single small-dimensioned electron beam is practicable for contactless testing. However, a single electron beam cannot hold both an input signal at a desired level at one address and also go to other coordinate addresses to, for example, set other input conditions of the circuit. Moreover, testing circuits with an electron beam presents difficulties in deenergizing or isolating circuits not being tested while energizing the particular segment or module under test.
The present invention overcomes these difficulties and disadvantages. It permits one or more input conditions to be set by an electron beam and held at a desired level while the electron beam sets other input and output electrical characteristics and the input and/or output electrical characteristics are tested. It permits contactless testing of a single circuit module while the other circuit modules on an integrated circuit chip are maintained in a deenergized condition.